/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "../core/defines.v"
`include "axi_defines.v"
`timescale 1ns/1ps

module axi_addr_dec(
	input	wire[`MemAddrBus]		req_addr_i,

	output	wire					s0_sel_o,
	output	wire					s1_sel_o,
	output	wire					s2_sel_o,
	output	wire					s3_sel_o,
	output	wire					s4_sel_o,
	output	wire					s5_sel_o,
	output	wire					s6_sel_o,
	output	wire					s7_sel_o
	);

	assign s0_sel_o = (req_addr_i < `ROM_BASE);
	assign s1_sel_o = (req_addr_i >= `ROM_BASE) & (req_addr_i < `UART_BASE);
	assign s2_sel_o = (req_addr_i >= `UART_BASE) & (req_addr_i < `GPIO_BASE);
	assign s3_sel_o = (req_addr_i >= `GPIO_BASE) & (req_addr_i < `SDRAM_BASE);
	assign s4_sel_o = (req_addr_i >= `SDRAM_BASE) & (req_addr_i < `ADDR_END);
	assign s5_sel_o = 1'b0;
	assign s6_sel_o = 1'b0;
	assign s7_sel_o = 1'b0;

endmodule